/*//////////////////////////////////////////////////////////////////////////////////////////
					ADC
//////////////////////////////////////////////////////////////////////////////////////////*/
void ADC_INI(void);
void ADC_START(void);
///////////////////////////////////////////////////////////////////////////////////////////
void ADC_INI (void) 	// inicializar ADC
{
	ADMUX|=(0<<REFS1)|(1<<REFS0)|(0<<MUX2)|(0<<MUX1)|(0<<MUX0);   				//Internal 2.56V Voltage Reference with external capacitor at AREF pin
	ADCSRA|=(1<<ADEN);																//enable ADC 
}
void ADC_START(void)
{
	ADCSRA|= (1<<ADSC);																//Start conversion
}
/*-------------------------------------------------------------------------------------------------------
				ADC Informacion de Fabricante
---------------------------------------------------------------------------------------------------------

		Bit 7 6 5 4 3 2 1 0
----	REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ----> "ADMUX"

		REFS1:0: Reference Selection Bits
		These bits select the voltage reference for the ADC, as shown in Table 83. If these bits are
		changed during a conversion, the change will not go in effect until this conversion is complete
		(ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external
		reference voltage is being applied to the AREF pin.
			
				Voltage Reference Selections for ADC

				REFS1-REFS0		 Voltage Reference Selection
				0 0 		AREF, Internal Vref turned off
				0 1 		AVCC with external capacitor at AREF pin
				1 0 		Reserved
				1 1 		Internal 2.56V Voltage Reference with external capacitor at AREF pin

		ADLAR: ADC Left Adjust Result

		MUX4:0: Analog Channel and Gain Selection Bits
		The value of these bits selects which combination of analog inputs are connected to the ADC.
		These bits also select the gain for the differential channels. See Table 84 for details. If these bits
		are changed during a conversion, the change will not go in effect until this conversion is
		complete (ADIF in ADCSRA is set).
	

				MUX4..0 -Single Ended Input -	Positive Differential Input - 	Negative Differential Input - Gain

				00000 	ADC0
				00001 	ADC1
				00010 	ADC2
				00011 	ADC3 	N/A
				00100 	ADC4
				00101 	ADC5
				00110 	ADC6
				00111 	ADC7
				01000 			ADC0		ADC0 		10x
				01001 			ADC1 		ADC0 		10x
				01010 			ADC0 		ADC0 		200x
				01011 			ADC1 		ADC0 		200x
				01100 			ADC2 		ADC2 		10x
				01101 			ADC3 		ADC2 		10x
				01110 			ADC2 		ADC2 		200x
				01111 			ADC3 		ADC2 		200x
				10000 			ADC0 		ADC1 		1x
				10001 			ADC1 		ADC1 		1x
				10010 	N/A 	ADC2 		ADC1 		1x
				10011 			ADC3		ADC1 		1x
				10100 			ADC4 		ADC1 		1x
				10101 			ADC5 		ADC1 		1x
				10110 			ADC6 		ADC1 		1x
				10111 			ADC7 		ADC1 		1x
				11000 			ADC0 		ADC2 		1x
				11001 			ADC1 		ADC2 		1x
				11010 			ADC2 		ADC2 		1x
				11011 			ADC3 		ADC2 		1x
				11100 			ADC4 		ADC2 		1x
				11101 			ADC5 		ADC2 		1x
				11110 	1.22V (VBG) 		N/A
				11111 	0 V (GND)



		Bit 7 6 5 4 3 2 1 0
----	ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0-------->  "ADCSRA"

		ADEN: ADC Enable
		Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the
		ADC off while a conversion is in progress, will terminate this conversion.

		ADSC: ADC Start Conversion
		In Single Conversion mode, write this bit to one to start each conversion. In Free Running Mode,
		write this bit to one to start the first conversion. The first conversion after ADSC has been written
		after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,
		will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization
		of the ADC.

		ADSC will read as one as long as a conversion is in progress. When the conversion is complete,
		it returns to zero. Writing zero to this bit has no effect.

		ADATE: ADC Auto Trigger Enable
		When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion
		on a positive edge of the selected trigger signal. The trigger source is selected by setting
		the ADC Trigger Select bits, ADTS in SFIOR.

		 ADIF: ADC Interrupt Flag
		This bit is set when an ADC conversion completes and the Data Registers are updated. The
		ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.
		ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively,
		ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-
		Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI
		instructions are used.

		ADIE: ADC Interrupt Enable
		When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt
		is activated.

		ADPS2:0: ADC Prescaler Select Bits
		These bits determine the division factor between the XTAL frequency and the input clock to the
		ADC.
						Prescaler Selections

					ADPS2-ADPS0   Division Factor
						0 0 0		2
						0 0 1   	2
						0 1 0   	4
						0 1 1   	8
						1 0 0		16
						1 0 1 		32
						1 1 0 		64
						1 1 1 		128

		Bit 7 6 5 4 3 2 1 0
----	ADTS2 ADTS1 ADTS0 - ACME PUD PSR2 PSR10 ---------> "SFIOR"

		ADTS2:0: ADC Auto Trigger Source
		If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
		an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion
		will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trigger
		source that is cleared to a trigger source that is set, will generate a positive edge on the
		trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running
		mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set

				Table 86. ADC Auto Trigger Source Selections
				ADTS2 ADTS1 ADTS0 Trigger Source
				0 0 0 Free Running mode
				0 0 1 Analog Comparator
				0 1 0 External Interrupt Request 0
				0 1 1 Timer/Counter0 Compare Match
				1 0 0 Timer/Counter0 Overflow
				1 0 1 Timer/Counter1 Compare Match B
				1 1 0 Timer/Counter1 Overflow
				1 1 1 Timer/Counter1 Capture Event

		Res: Reserved Bit
		This bit is reserved for future use. To ensure compatibility with future devices, this bit must be
		written to zero when SFIOR is written.
-------------------------------------------------------------------------------------------------------*/
/*////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
				ADC
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////*/

